module MFUNC_TOP ( /*AUTOARG*/
   // Outputs
   reg_MFUNC_TOP_rd_data, params_start, params_ch0_start,
   params_ch1_start, params_ch2_start, params_ch3_start,
   params_saddr_l, params_saddr_h, params_daddr_l, params_daddr_h,
   params_data_len, params_wr_mode, params_rd_mode, params_test,
   // Inputs
   clk, rst_n, reg_MFUNC_TOP_wr_en, sub_reg_addr, reg_wr_data,
   params_data_done, params_test_ro
   );
input         clk;
input         rst_n;
input         reg_MFUNC_TOP_wr_en;
input  [11:0] sub_reg_addr;
input  [31:0] reg_wr_data;
output [31:0] reg_MFUNC_TOP_rd_data;
output  [1:0]   params_start;
output  [0:0]   params_ch0_start;
output  [1:0]   params_ch1_start;
output  [1:0]   params_ch2_start;
output  [0:0]   params_ch3_start;
output  [7:0]   params_saddr_l;
output  [7:0]   params_saddr_h;
output  [7:0]   params_daddr_l;
output  [7:0]   params_daddr_h;
output  [7:0]   params_data_len;
output           params_wr_mode;
output           params_rd_mode;
input            params_data_done;
output  [15:0]   params_test;
input   [15:0]   params_test_ro;
/////////////////////////////////////////////////////
reg  [31:0]   reg_MFUNC_TOP_rd_data;
reg  [7:0]   reg_000;
reg  [7:0]   reg_001;
reg  [7:0]   reg_002;
reg  [7:0]   reg_003;
reg  [7:0]   reg_004;
reg  [7:0]   reg_005;
reg           reg_006;
reg           reg_007;
reg           reg_008;
reg  [7:0]   reg_009;
reg  [7:0]   reg_00a;
reg  [7:0]   reg_00b;
reg  [7:0]   reg_00c;
wire          wr_000_en;
wire          wr_001_en;
wire          wr_002_en;
wire          wr_003_en;
wire          wr_004_en;
wire          wr_005_en;
wire          wr_006_en;
wire          wr_007_en;
wire          wr_008_en;
wire          wr_009_en;
wire          wr_00a_en;
wire          wr_00b_en;
wire          wr_00c_en;
assign          wr_000_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h000));
assign          wr_001_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h001));
assign          wr_002_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h002));
assign          wr_003_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h003));
assign          wr_004_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h004));
assign          wr_005_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h005));
assign          wr_006_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h006));
assign          wr_007_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h007));
assign          wr_008_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h008));
assign          wr_009_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h009));
assign          wr_00a_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h00a));
assign          wr_00b_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h00b));
assign          wr_00c_en=(reg_MFUNC_TOP_wr_en&&(sub_reg_addr==12'h00c));
/////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_000<=8'd0;
    end
    else if (wr_000_en) begin
       reg_000<=reg_wr_data;
    end
end
assign  params_start=reg_000[1:0];
assign  params_ch0_start=reg_000[2];
assign  params_ch1_start=reg_000[4:3];
assign  params_ch2_start=reg_000[6:5];
assign  params_ch3_start=reg_000[7];
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_001<=8'h00;
    end
    else if (wr_001_en) begin
       reg_001<=reg_wr_data;
    end
end
assign  params_saddr_l=reg_001;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_002<=8'h00;
    end
    else if (wr_002_en) begin
       reg_002<=reg_wr_data;
    end
end
assign  params_saddr_h=reg_002;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_003<=8'h00;
    end
    else if (wr_003_en) begin
       reg_003<=reg_wr_data;
    end
end
assign  params_daddr_l=reg_003;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_004<=8'h00;
    end
    else if (wr_004_en) begin
       reg_004<=reg_wr_data;
    end
end
assign  params_daddr_h=reg_004;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_005<=8'h01;
    end
    else if (wr_005_en) begin
       reg_005<=reg_wr_data;
    end
end
assign  params_data_len=reg_005;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_006<=1'd0;
    end
    else if (wr_006_en) begin
       reg_006<=reg_wr_data;
    end
end
assign  params_wr_mode=reg_006;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_007<=1'd0;
    end
    else if (wr_007_en) begin
       reg_007<=reg_wr_data;
    end
end
assign  params_rd_mode=reg_007;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_008<=1'd0;
    end
    else  begin
       reg_008<=params_data_done;
    end
end
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_009<=8'h09;
    end
    else if (wr_009_en) begin
       reg_009<=reg_wr_data;
    end
end
assign  params_test[7:0]=reg_009;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_00a<=8'h0a;
    end
    else if (wr_00a_en) begin
       reg_00a<=reg_wr_data;
    end
end
assign  params_test[15:8]=reg_00a;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_00b<=8'h0b;
    end
    else  begin
       reg_00b<=params_test_ro[7:0];
    end
end
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_00c<=8'h0c;
    end
    else  begin
       reg_00c<=params_test_ro[15:8];
    end
end
always @( * )
begin
    case(sub_reg_addr) 
    12'h000 : reg_MFUNC_TOP_rd_data=reg_000;
    12'h001 : reg_MFUNC_TOP_rd_data=reg_001;
    12'h002 : reg_MFUNC_TOP_rd_data=reg_002;
    12'h003 : reg_MFUNC_TOP_rd_data=reg_003;
    12'h004 : reg_MFUNC_TOP_rd_data=reg_004;
    12'h005 : reg_MFUNC_TOP_rd_data=reg_005;
    12'h006 : reg_MFUNC_TOP_rd_data=reg_006;
    12'h007 : reg_MFUNC_TOP_rd_data=reg_007;
    12'h008 : reg_MFUNC_TOP_rd_data=reg_008;
    12'h009 : reg_MFUNC_TOP_rd_data=reg_009;
    12'h00a : reg_MFUNC_TOP_rd_data=reg_00a;
    12'h00b : reg_MFUNC_TOP_rd_data=reg_00b;
    12'h00c : reg_MFUNC_TOP_rd_data=reg_00c;
    default : reg_MFUNC_TOP_rd_data=32'h5a5a_a5a5;
    endcase
end
endmodule
